Single Chip Secure Environment

SEcube™ is the smallest reconfigurable silicon combining three main cores in a single-chip design. Low-power ARM Cortex-M4 processor, a flexible and fast Field-Programmable-Gate-Array (FPGA), and an EAL5+ certified Security Controller (SmartCard) are embedded in an extremely compact package. This makes it a unique security environment where each function can be optimised, executed, and verified on its proper hardware device.


SEcube™ Secure Environment

  • STM32F4 – ARM® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART AcceleratorTM) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions – FLASH 2 MB – RAM 256 KB
  • Security Controller SLJ52G – JavaCard Platform, including ePassport and eSign applets
  • Supported standards: JC 3.0, GP 2.2, ICAO BAC, SAC, AA, BSI- TR03110 v1.11 EAC, ISO 18013 BAP, EAP config 1-4 – 128 Kbyte EEPROM – DES, 3DES, AES up to 256-bit – RSA up to 2048-bit, ECC up to 521-bit
  • Certified Common Criteria CC EAL5+ high
  • FPGA – MachXO2-7000 – 6864 LUTs – Ultra Low Power Device (65 nm process, 19 μW standby power, programmable low swing differential I/Os, Stand-by mode and other power saving options)
  • Embedded and distributed memory
    – 240 Kbits SysMEMTM embedded blocks RAM
    – 54 Kbits distributed RAM
    – Dedicated FIFO control logic
  • 256 Kbits On-Chip User Flash Memory
  • Wide Frequency range (10 MHz to 400 MHz)
  • Non-Volatile infinitely reconfigurable
  • In-field logic configuration while system operates
  • Interfaces
    – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
    – 47 FPGA I/Os

Typical Application Diagrams